Coleco ADAM MIOCC pinouts

These were sent to me by Dr. Rich Drushel a while back.

Haven't been able to do anything with them yet, so I

thought I would share.


MIOC Pinouts (U7):

/X = active low

Pin Signal I/O Description

1 Vcc input +5V supply

2 RA7 output 8th bit DRAM refresh;

gated out by /ADDRBUFEN

3 BA15 input Address BUS bit 15

4 BA14 input Address BUS bit 14

5 BA13 input Address BUS bit 13

6 /CVRST input ColecoVision reset switch

7 BD0 I/O Data BUS bit 0

8 BD1 I/O Data BUS bit 1

9 BD2 I/O Data BUS bit 2

10 BD3 I/O Data BUS bit 3

11 /BWR' input made by complex logic from MA5,

/IORQ, and A10

12 BA6 input Address BUS bit 7

13 BA7' input BA7, gated in by /ADDRBUFEN

14 /IORQ input IO Request - Z80 Control

15 /WAIT input Wait - Z80 control

16 /BUSAK input BUS Acknowledge - Z80 Control

17 /DMA input Asserted by Master 6801 to access


18 /BUSRQ output BUS Request - Z80 Control

19 /EOS_ENABLE output selects/deselects EOS ROM

20 /NET_RST output reset signal for ADAMNet

21 GND --- Ground

22 /AUX_DECODE1 output selects/deselects OS7 ROM

23 /RST output reset signal for the Master 6801

24 /CPRST ??? not connected on schematic;

reset for something

25 /PBRST input ADAM reset switch

26 /AUX_ROM_CS output selects/deselects expansion

ROM (center slot)

27 /ADDRBUFEN output enables/disables /BRD, /BWR,


(disabled during DMA cycle)

28 /BOOT_ROM_CS output selects/deselects SmartWriter ROM

29 /245EN output enables/disables BD0-BD7

(disabled during DMA cycle)

30 /IS3 output input to Master 6801

31 /OS3 input output to Master 6801

32 /BMREQ input Memory Request - Z80 Control

33 /BRD input Z80 Control Signal

34 /BRFSH input Z80 Control Signal

35 /BM1 input Z80 Machine Cycle 1

36 B(phi) input Z80 clock

37 MUX output multiplexing signal for

DRAM Refresh

38 /RAS1 output row address strobe, base 64K RAM

39 /CAS1 output column address strobe, base 64K RAM

40 /CAS2 output column address strobe, 64K XRAM